The assignee of the present invention is the assignee of a set of patents describing three dimensional packaging arrangements for computer systems. The present invention is an improvement upon the prior art described in those patents. The patents of interest include U.S. Pat. Nos. 5,065,277, 5,053,856, and 5,079,619, each of which is expressly incorporated by reference herein.
U.S. Pat. No. 5,065,277 discloses a three dimensional arrangement for packaging planar arrays of circuit components. Each planar array includes a multi-chip module supported by a substrate. The multi-chip module includes a set of integrated circuits supported by an insulator that also supports metal interconnect used to electrically connect the integrated circuits. Typically, the insulator is formed of polyimide and the interconnect is formed of copper. The multi-chip module is positioned on a substrate. The substrate includes vias which extend from the first planar surface of the substrate, through the substrate, to the second planar surface of the substrate. The vias on the first planar surface of the substrate are used for electrical connection to the metal interconnect of the multi-chip module.
In the prior art, this combination of a multi-chip module and a substrate is positioned within a shell. The shell includes connecting vias to electrically connect to the vias of the second planar surface of the substrate. In this configuration, the connecting vias of the shell can be used for electrical connection to another similarly configured module. Namely, the connecting vias can be electrically connected to a second multi-chip module and substrate which itself is positioned within a shell. As explained in U.S. Pat. No. 5,065,277, such a configuration can be used to form a computer system that includes sixteen processors and 0.5 gigabytes of random access memory in a volume approximately four inches by four inches by one inch.
Different devices for cooling the apparatus of U.S. Pat. No. 5,065,277 are described in U.S. Pat. Nos. 5,079,619 and 5,053,856. The operation of the cooling devices is inherently limited in view of the fact that the cooling devices are positioned against the multi-chip module substrate. As a result, heat generated on the multi-chip module must first migrate through the multi-chip module substrate and then be removed by the cooling devices.
It would be highly desirable to improve the high density electronic packages of U.S. Pat. Nos. 5,065,277, 5,053,856, and 5,079,619 by further reducing the size of the packages to facilitate improved component density, by reducing their cost, and by improving their thermal performance.